Computer Organization and Architecture
·
Computer Architecture refers to those attributes of a
system that have a direct impact on the logical execution of a program.
Examples:
o
the instruction set
o
the number of bits used
to represent various data types
o
I/O mechanisms
o
memory addressing techniques
·
Computer Organization refers to the operational units and their
interconnections that realize the architectural specifications. Examples are
things that are transparent to the programmer:
o
control signals
o
interfaces between computer
and peripherals
o
the memory technology being used
·
So, for example,
the fact that a multiply
instruction is available is a computer
architecture issue. How that multiply is implemented is a computer
organization issue.
•
Architecture is those
attributes visible to the programmer
o
Instruction set, number of bits used for data representation, I/O mechanisms,
addressing techniques.
o
e.g. Is there a multiply
instruction?
•
Organization is how features are
implemented
o
Control signals, interfaces, memory technology.
o
e.g. Is there a hardware
multiply unit or is it
done by repeated addition?
•
All Intel x86 family share the same basic
architecture
•
The IBM System/370 family share the same basic architecture
•
This gives code compatibility
o
At least backwards
•
Organization differs between
different versions
§ Indicated by an interrupt signal
o
If no interrupt, fetch next instruction
o
If interrupt pending:
§ Suspend execution of current program
§ Save context
§ Set PC to start
address of interrupt handler routine
§ Process interrupt
§ Restore context and continue interrupted program
Fig: Transfer of control
via interrupts
Fig: Instruction cycle state diagram, with
interrupts
• Multiple Interrupts
o
Disable interrupts (approach #1)
§ Processor will ignore further
interrupts whilst processing one interrupt
§ Interrupts remain
pending and are checked after first interrupt has been processed
§ Interrupts handled
in sequence as they occur
o
Define priorities (approach #2)
§ Low priority interrupts can be
interrupted by higher priority interrupts
§
When higher priority
interrupt has been processed, processor returns to previous
interrupt
PCI
·
PCI is a popular high bandwidth, processor independent
bus that can function as mezzanine or peripheral bus.
·
PCI delivers better system performance for high speed I/O subsystems (graphic display
adapters, network interface controllers, disk controllers etc.)
·
PCI is designed to support a variety of microprocessor
based configurations including both single
and multiple processor system.
·
It makes use of synchronous timing and centralised arbitration scheme.
·
PCI may be configured as a
32 or 64-bit bus.
·
Current Standard
o
up to 64 data lines at 33Mhz
o
requires few chips to implement
o
supports other buses
attached to PCI bus
o
public domain, initially
developed by Intel to
support Pentium-based systems
o
supports a variety
of microprocessor-based configurations, including multiple processors
o
uses synchronous timing
and centralized arbitration
Note: Bridge acts as a data buffer so that the speed of the PCI bus may differ from that of the processor’s I/O capability
Note: In a multiprocessor system,
one or more PCI configurations may be connected by bridges to the processor’s
system bus.
PCI Bus Lines
•
Systems lines
o
Including clock and reset
•
Address & Data
o
32 time mux lines for address/data
o
Interrupt & validate
lines
•
Interface Control
•
Arbitration
o
Not shared
o
Direct connection to PCI bus arbiter
• 
Error lines
•
Interrupt lines
o
Not shared
•
Cache support
• 64-bit Bus Extension
o
Additional 32 lines
o
Time multiplexed
o
2 lines to enable devices to agree to use 64-bit
transfer
•
JTAG/Boundary Scan
o
For testing procedures
PCI Commands
• Transaction between
initiator (master) and target
• Master claims
bus
•
Determine type of transaction
o
e.g. I/O read/write
•
Address phase
• One or more data phases
PCI Enhancements: AGP
AGP – Advanced Graphics Port
o Called a port, not a bus because it only connects 2 devices
-
Fetch Instructions
-
Interpret Instructions
-
Fetch Data
-
Process Data
-
Write Data
·
A small amount of internal memory, called the registers, is needed by
the CPU to fulfill these requirement
·
Components of the CPU
-
Arithmetic and Logic Unit (ALU): does the actual computation or
processing of data
-
Control Unit (CU): controls
the movement of data and instructions into and
out of the CPU and controls the operation of the ALU.
Register Organization
·
Registers are at top of the memory
hierarchy. They serve two
functions:
1.
User-Visible Registers - enable the machine- or assembly-language
programmer to minimize main-memory references by optimizing use of registers
2. Control and Status
Registers - used by the control unit to control the operation
of the CPU and by privileged,
OS programs to control the execution of programs
User-Visible Registers
Categories of Use
-
General Purpose registers - for variety
of functions
-
Data registers - hold data
-
Address registers - hold address
information
-
Segment pointers - hold base address of the segment
in use
-
Index registers - used for
indexed addressing and may be auto
indexed
-
Stack Pointer - a dedicated
register that points
to top of a stack.
Push, pop, and other stack instructions need not
contain an explicit stack operand.
-
Condition Codes (flags)
Design Issues
·
Completely general-purpose registers
or specialized use?
-
Specialized registers save bits in instructions because
their use can be implicit
-
General-purpose registers are more flexible
-
Trend is toward use of specialized registers
·
Number of registers
provided?
-
More registers require more operand specifier bits in instructions
-
8 to 32 registers appears
optimum (RISC systems
use hundreds, but are a completely different approach)
·
Register Length?
-
Address registers must be long enough to hold the largest address
-
Data registers should be able to hold
values of most data types
-
Some machines allow two contiguous registers for
double-length values
·
Automatic or manual save of condition codes?
-
Condition restore is usually automatic upon call return
-
Saving condition code registers may be automatic upon call instruction, or may be manual
Control and Status
Registers
·
Essential to instruction execution
-
Program Counter (PC)
-
Instruction Register (IR)
-
Memory Address Register
(MAR) - usually
connected directly to address lines of bus
-
Memory Buffer Register (MBR) - usually
connected directly to data lines of bus
·
Program Status Word (PSW) - also essential, common fields or flags contained include:
-
Sign - sign bit of last arithmetic operation
-
Zero - set when result
of last arithmetic operation
is 0
-
Carry - set if last op resulted in a carry into or borrow out of a high-order
bit
-
Equal - set if
a logical compare result is equality
-
Overflow - set when last arithmetic operation
caused overflow
-
Interrupt Enable/Disable - used to enable
or disable interrupts
-
Supervisor - indicates
if privileged ops can be used
·
Other optional
registers
-
Pointer to a block of memory containing additional status info (like process control blocks)
-
An interrupt vector
-
A system stack
pointer
-
A page table pointer
-
I/O registers
·
Design issues
-
Operating system support in CPU
-
How to divide allocation of control information between CPU registers
and first part of main memory (usual
tradeoffs apply)
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